1. Field of the Invention
This invention relates to semiconductor memories, particularly to non-volatile memories using variable threshold transistors.
2. Description of the Prior Art
In the prior art, non-volatile memories have been fabricated using P-channel variable threshold transistors. The P-channel variable threshold transistor has a large hysteresis window in the enhancement mode region and a small window in the depletion mode region. To avoid memory sensing problems, the P-channel variable threshold transistors are operated or written utilizing the available hysteresis window in the enhancement mode region such as from -2 volts to -10 volts. A desirable structure to insure that the variable threshold P-channel transistor operates in the enhancement mode region is described in U.S. Pat. No. 3,836,894, issued on Sept. 17, 1974 to James R. Cricchi, entitled MNOS/SOS Random Access Memory and assigned to the assignee herein. The patent to Cricchi describes a drain source protected P-channel transistor wherein a thick insulation layer next to the source and drain diffusions keep the transistor exhibiting a threshold voltage of -2 volts or thereabouts while a thin insulation layer between the source thick insulation regions and between the drain provides variable threshold characteristics. The memory transistor when read exhibits enhancement mode characteristics by reason of the thick insulation layer adjacent the drain and source diffusions. From a circuit standpoint, the transistor never goes into the depletion mode such as a V.sub.GS of +1 volt but remains in the enhancement mode having a voltage such as -2 volts for one memory state. In the other memory state the transistor may exhibit a threshold voltage of -11 volts, for example.
For high speed non-volatile memories, N-channel technology is desirable because N-channel transistors are inherently faster than P-channel transistors. In N-channel transistors the majority carrier is electrons while in P-channel transistors the majority carrier are holes having a lower mobility constant.
A non-volatile memory utilizing N-channel variable threshold transistors has a small voltage window in the enhancement mode region such as from 4 volts to 1 volt as compared to the P-channel variable threshold transistor which has a large voltage window from -2 volts to -11 volts. However, while the voltage window in the depletion mode in a P-channel variable threshold transistor is from 2 volts to 0 volts, the voltage window in the depletion mode in an N-channel variable threshold transistor is from 1 volt to -10 volts with a window of 11 volts.
It is therefore desirable to provide an N-channel non-volatile memory which utilizes N-channel transistors operating in the depletion region.
It is further desirable to provide a convenient way to read the memory state of a depletion mode N-channel variable threshold device.
It is desirable to provide an N-channel transistor structure which exhibits a variable threshold characteristic in the substrate extending from the source to a predetermined distance from the drain.
It is desirable to provide an N-channel variable threshold transistor memory which does not require the full value of its hysteresis window or variable threshold voltage swing for sensing the information stored in the transistor.
It is further desirable to provide an N-channel variable threshold transistor memory which may have its information read without causing a read-disturb effect to individual transistors.